1. Technical Field
The present invention relates to a semiconductor circuit, and more particularly, to an impedance calibration circuit which may be used in a semiconductor apparatus, specifically in a semiconductor memory apparatus.
2. Related Art
As an electronic system operates at a high speed, data is also transmitted at a high speed across semiconductor circuits which constitute the system.
In order to achieve high data transmission, matching the impedance of a data transmission path with the output impedance of an output circuit is necessary.
In particular, the semiconductor memory apparatus, which is a representative example of a semiconductor circuit, may include an impedance calibration circuit to match output impedance with the impedance of a transmission path by calibrating the output impedance.
The impedance calibration circuit may perform an impedance calibration operation in response to an externally inputted impedance calibration command ZQC.
According to an operation standard for a semiconductor memory related to impedance calibration, the impedance calibration command ZQC may be defined by a combination of CS/, RAS/, CAS/and WE/.
The impedance calibration command ZQC may be classified as a ZQ calibration long (ZQCL) and a ZQ calibration short (ZQCS), and the ZQCL is distinguished from the ZQCS by an address signal A<10>.
The ZQCL may be provided in an initial operation of a semiconductor circuit. The ZQCL is a command that instructs to perform a long-term impedance calibration operation (such as, for example, 256 tCK or 512 tCK) as compared with the ZQCS.
Meanwhile, the ZQCS may be provided after the ZQCL is completed. The ZQCS is a command that instructs to perform a short-term impedance calibration operation (such as, for example, 64 tCK) as compared with the ZQCL.
FIG. 1 is an illustration of an example of a conventional impedance calibration circuit, which includes a control unit 10, a timer counter 20, and an impedance calibration signal generation unit 30.
The control unit 10 may generate a plurality of internal commands iZQCS, ZQINIT and ZQOPER. The plurality of internal commands iZQCS, ZQINIT and ZQOPER instruct to perform an impedance calibration operation in response to an impedance calibration command ZQC, an address signal A<10> and a reset signal RESETB.
Among them, the internal command iZQCS may be generated by the ZQCS and the internal commands ZQINIT and ZQOPER may be generated by the ZQCL.
The timer counter 20 may generate an operation control signal CAL_OPER that prescribes the duration of time for the impedance calibration operation in response to the plurality of internal commands iZQCS, ZQINIT and ZQOPER by using a clock signal CLK.
The impedance calibration signal generation unit 30 may operate for a predetermined time defined by the operation control signal CAL_OPER to generate impedance calibration signals PCODE<0:N> and NCODE<0:N>.
The impedance calibration signal generation unit 30 may include a plurality of comparators 31 and 34, a plurality of counters 32 and 35, and a plurality of digital-to-analog converters 33, 36 and 37.
The digital-to-analog converters 33 and 36 are designed by modeling a pull-up driver of a data output driver, and the digital-to-analog converter 37 is designed by modeling a pull-down driver of the data output driver.
The digital-to-analog converter 33 may be coupled to an external resistor RZQ through a pad ZQ.
The impedance calibration signal generation unit 30 may change the values of the impedance calibration signals PCODE<0:N> such that a voltage level (such as, for example, a ZQ node voltage) obtained by converting the impedance calibration signals PCODE<0:N> in the form of a digital code through the digital-to-analog converter 33 is substantially identical to a reference voltage.
Furthermore, the impedance calibration signal generation unit 30 may input the impedance calibration signals PCODE<0:N> to the digital-to-analog converter 36, and may change the values of the impedance calibration signals NCODE<0:N> such that a voltage level (such as, for example, a NA node voltage) obtained by converting the impedance calibration signals NCODE<0:N> through the digital-to-analog converter 37 is substantially identical to the reference voltage.
FIG. 2 is a timing diagram illustrating impedance calibration operation timing obtained by the conventional impedance calibration signal generation unit 30. Referring to FIG. 2, the impedance calibration operation may be performed for a predetermined time defined by the internal commands ZQINIT and ZQOPER generated in response to the ZQCL in an initial operation of the semiconductor circuit.
The impedance calibration signals PCODE<0:N> and NCODE<0:N> changed through the impedance calibration are provided to a data output driver, so that the output impedance of the semiconductor circuit is calibrated to be substantially identical to a target impedance, that is, the impedance of the external resistor RZQ.
As described above, after the impedance calibration operation in response to the ZQCL is completed, an impedance calibration operation may be performed with a random period of time defined by the internal command iZQCS generated in response to the ZQCS.
Meanwhile, since the semiconductor circuit is used in various application fields, the semiconductor circuit has various temperature conditions according to regions and application in which the semiconductor circuit is used.
For example, in the case where a semiconductor memory in a vehicle navigation system is used in an extremely high temperature region or low temperature region, a temperature change may occur due to an increase or decrease in internal temperature while a vehicle is running as compared with the initial temperature when the vehicle is first started up.
FIG. 2, is an illustration of an exemplary situation showing that after the impedance calibration operation in response to the ZQCL is completed, a temperature change may occur in the temperature range as indicated by P_T1 to P_T4.
However, according to the conventional art, the impedance calibration operation in response to the ZQCS may be performed regardless of the above-described temperature change.
Therefore, as in FIG. 3 which illustrates a change in an impedance value according to the conventional art, after the output impedance of the semiconductor circuit is calibrated to a normal value, such as a value substantially identical to the impedance of the external resistor RZQ, through the impedance calibration operation in response to the ZQCL, impedance miss-matching, in which impedance changes like Case A or Case B, may occur due to the impedance calibration operation in response to the ZQCS, which does not consider a temperature change.